Chalmers University and the University of Edinburgh plan to establish a
cooperation on the future development of chip multiprocessors (CMPs), an
important emerging class of parallel computer. The partnership will focus on
issues such as the support for shared memory consistency models and the
difficult task of writing parallel programs for these new machines, with an
emphasis on embedded architectures. Work on consistency models will include
hardware oriented techniques such as coherence protocols, software oriented
techniques such as compiler directed coherence, and hybrid approaches
combining the best of both worlds.
 
The group at Chalmers University has an
established track record in research on the performance analysis,
implementation and optimisation of hardware coherence protocols and some
compiler/hybrid techniques to improve performance. They have also analysed
the power requirements of coherence mechanisms in the context of chip
multiprocessors. The compiler and architecture group at Edinburgh has
extensive expertise on software support for architectural mechanisms such as
speculative multithreading, distributed invalidation on shared memory
computers and autoparallelisation. They also have experience of compiler
optimisation specifically for embedded computing. The ultimate aim of the
project is to bring together these two groups to characterise the issues for
embedded shared memory multiprocessing and explore the full benefit of global
static analysis at compile-time, mechanisms to pass information collected by
the compiler to the hardware and the means for the hardware to effectively
exploit it.

The goal of this collaboration is to explore the potential for a combined
hardware/software approach to shared memory consistency for embedded chip
multiprocessors and agree on a common infrastructure for investigating the
issues of interest to both groups. Common ground that needs to be established
includes the choice of programming model (e.g. thread based with a relaxed
consistency model), relevant benchmarks for evaluation (e.g. splash2, SPEC OMP 2001),
compiler platform and simulation platform. The simulation platform is
most likely to be SIMICS, developed at the Swedish Institute for computer
science and currently marketed by Virtutech, which is already in use at
Edinburgh. SIMICS is a candidate for the common European simulation platform,
with micro-architectural extensions developed at Chalmers.

The collaboration will be established first by a meeting of the project
leaders at Edinburgh followed by an intensive visit (e.g. one to two
months) to Chalmers by Dr. Ashby. A longer initial visit will provide the opportunity
to iron out any initial difficulties and establish a firm base for future collaboration in a rapidly
developing area that will be important to European research and economic
development in the short to medium-term future. The estimate for the kick-off
meeting is 1.5K euros for a visit of up to two weeks, followed by 1.5K euros per month
for the longer trip to Sweden. In addition we require funds to attend the four annual
HiPEAC cluster meetings at 700 euros per meeting, giving a total of 7.3K euros.

Dr. Tom Ashby - University of Edinburgh