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Characterization of Commercial Workloads in Chip Multiprocessor Architectures970 / Accepted / Finalized / Final evaluation Due to the increase in the integration capacity and the power density limits in the chip, vendors have decided to include several cores in one chip, calling this design chip multiprocessor. Besides this new technological framework, new work environments have appeared and some applications have grown more important. Some examples could be web servers (Apache), execution environments (J2EE, .NET), and database management systems (MySQL, DB2). All these applications should be used with the more traditional applications to evaluate the performance of the new execution environments. In this cluster, emergent applications will be characterized from the point of view of communication and synchronization in order to know their tolerance to the execution latency and their needs regarding productivity. Since the communication latency has been reduced and the bandwidth has been increased from the traditional multiprocessor systems, the design tradeoffs in a chip multiprocessor should be evaluated. Taking into account the communication and synchronization degree among the threads in all these applications, memory hierarchies and coherence and management contents mechanisms will be proposed. This cluster is an extension of the cluster called "Accurate and Complexity-Effective Coherence Predictors" where different mechanisms were evaluated to predict which processor was going to be the next owner of a block based on the execution of critical sections. This work was done for the Splash2 suite and a small part of it was presented in: Ana Bosque, Víctor Viñals, José M. Llabería, and Per Stenström, "Accurate and Complexity-Effective Coherence Predictors", ACACES 2005 Poster Abstracts ISBN: 90 382 0802 2, L'Aquila, Italy, July 24-30 2005 As it was interesting to extend the work for commercial workloads, an analysis of these applications was decided to be done in advance in order to understand their main characteristics. The ongoing work is collected in: Ana Bosque, Víctor Viñals, Pablo Ibañez, Per Stenström, and Jose M. Llaberia, "Cache Miss Characterization of Commercial Workloads", ACACES 2006 Poster Abstracts ISBN: 90 382 0981 9, L'Aquila, Italy, July 23-29 2006. Ana Bosque, Pablo Ibañez, Victor Viñals, Per Stenström, and Jose M. Llaberia, "Characterization of Apache webserver with SURGE and SPECweb2005", submitted to Euro-Par 2007. Research cluster Requested: € 7400 Requested: € 0 As this funding is for a whole year, it will cover four 2-day trips to cluster meetings plus two stays of a week at Chalmers for Ana Bosque, so 6 flights and 22 days of stay. As an estimate, a flight costs 500 EU and the hotel plus allowances plus other expenses per day is 200 EU. This adds up to: Flights: (6 x 500): 3000 EU Requested: 12 month(s) STENSTROM Per (Chalmers University of Technology) (--member--) VIñALS Victor (University of Zaragoza) (--member--) BOSQUE Ana (UPC) (--phd student--) LLABERIA Jose Maria (UPC) (--member--) IBAñEZ Pablo (University of Zaragoza) (--colleague--)
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