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Applications enabling the exploitation of heterogeneous architectures for the embedded marketNew Version:
------------------------------------ Old Version: In this cluster we will focus on algorithms and applications that could enable the use of the Cell BE processor for embedded systems. Application areas of interest include: * radio/video streaming Algorithms already under study apply to high resolution digital video (H.264/AVC), and bioinformatics (BLAST and Fasta). Algorithms and applications will be included in a software repository, as source code, with documentation and performance analysis on the Cell BE processor, and possibly other architectures. The Cell BE processor has 2 hardware contexts (PE, compatible with the PowerPC architecture) and 8 SPEs. Each SPE is a simple processor with its own small local memory (256 Kb.) that acts as a coprocessor. The instruction set of the SPEs is not compatible with the PowerPC architecture, except that the SIMD instructions are represented by a similar set of compiler intrisics. So, it is easy to port a code with SIMD instructions from the PowerPC architecture to the SPE instruction set. The current compiler infrastructures for the Cell BE processor include a modified GCC compiler from Sony and the XL compiler from IBM. We plan to use both infrastructures to optimize the applications using, where applicable, vectorization and parallelization. Vectorization on the Cell processor can be achieved by using SIMD instructions either in the PE or the SPEs. Parallelization usually will exploit some or all of the 8 SPEs attached to each PE. The fellowship is planned for UPC and he/she will be in charge of collecting the applications, use the compiler infrastructures available on the Cell BE processor to optimize them, and document the transformations done to the code and the performance obtained. After this initial period of 18 months collecting algorithms and applications for the Cell BE processor, we expect to extend the cluster for the next 18 months period, adapting the topic to the future research trends on this kind of architecture. Research cluster Requested: € 43200 Requested: € 21600 Travel: we plan to have meetings every 3 months, possibly in conjunction Fellowships: one fellowship for a person working on the topic at UPC: Total for 18 months (travel + fellowship): 21600 + 21600 = 43200 At the end of the period, we plan to extend this cluster for the next 18 months period. Requested: 18 month(s) BERNSTEIN David (IBM) (--member--) BILAS Angelos (FORTH) (--member--) GIL Marisa (UPC) (--member--) MARTORELL Xavier (UPC) (--member--) MENDELSON Bilha (IBM) (--member--) MORANCHO Enric (UPC) (--member--) NAVARRO Nacho (UPC) (--member--) RAMIREZ Alex (UPC) (--member--) ZAKS Ayal (IBM) (--member--) Eduard Ayguade, Mauricio Alvarez, Friman Sanchez, Carlos Villavieja,
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