Design of SIMD architectures exploiting regularity for the reduction of Process Variations

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Introduction:
Thales is a world leader in mission-critical information systems for defence and security, aerospace and transportation. The Embedded System Lab (ESL) at Thales Research and Technology elaborates and conducts research in computing architectures and programming tools to address Thales’ high performance and critical safety needs in embedded systems.
Description:
With the advent of 45nm technology nodes an below, architectures will be more and more exposed to effects of process variation. Process variations have both random components and systematic components. Design For Manufacturability (DFM), taking into account the increased variability of new processes, is a challenge of the next generations of technologies. Exploiting regularity at the architectural, structural, and geometrical levels is a promising approach for the optimization of manufacturability and the reduction of systematic variations in nanometer technologies. Many classes of architecture feature some kind of regularity at a coarse-grain level (e.g. MPSoC) or at a fine-grained level (e.g. SIMD architectures).
The object of this internship is to develop and to do the logic synthesis of a SIMD architecture in the context of DFM.
Required skills:
*PhD student in computer science, computer and/or electronic engineering.
*Good knowledge in computer architectures and micro architectures.
*Skills in VHDL/Verilog programming and logic synthesis.