optimized FPGA implementation of an algorithm through the HCE design flow

Click here to apply for this internship.

Affiliated to

Ylichron

Location

Ylichron offices, c/o ENEA Casaccia Research Center (Rome)

Timing

3 months from the starting date (orientative period, october - december 2010; could be changed according to special needs of the candidate)

Description

The candidate should use the high level synthesis HCE design flow to implement a critical kernel of her/his interest (coded as a C program) into an FPGA board equipped with high end Xilinx and/or Altera FPGAs. During the work, the candidate will be assisted by Ylichron experts to enable a very efficient implementation.
The aim of this internship is to guide a motivated PhD student toward an efficient way to implement algorithms onto FPGA, exploring both the algorithmic and the architectural design space.

<< Go back to Industrial Internship Home Page