Ph.D. Position at CEA LIST & UBS / Lab-STICC

Title: High-Level Synthesis for designing fault tolerant architectures on FPGA

Abstract
The candidate will have to propose radiation fault models from case studies and measurements on FPGA in a strongly disturbed environment.

From these models, mechanisms of tolerance to the faults, at the logical, algorithmic and system levels will be developed. These mechanisms will be integrated in a design approach of faults tolerant architectures based on the synthesis high-level. On the level algorithm, we have to qualify the algorithm behaviour in the presence of faults in order to know the tolerant parts. On the architecture level, the definition method of the hardware devices for fault detection is based on the traceability analysis of the transitory fault.

These models will be integrated in a tool to validate the approaches developed on complete measurement systems in strongly disturbed environments.

More details can be found at
http://www-instn.cea.fr/spip.php?page=Publication_Sujetuk&idSujet=1891&lang=en&langue=uk&id_rubrique=140

Contact: philippe.coussy@univ-ubs.fr / gwenole.corre@cea.fr