Scalable Interconnection Network and Cache Coherence using AMBA bus interface

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Description

In this project, you will start with a survey of scalable cache coherence techniques (e.g. directory-based) and scalable interconnection structures (e.g. packet-based), and then investigate the feasibility of implementing these with the AMBA bus interface structures in a many-core ARM SoC. You will model at least one interconnection network and one cache coherence technique using the high-level modeling (e.g. M5) as well as RTL modeling (e.g. Verilog).

Skills required:
- Phd student in computer science, computer/electrical/electronics engineering
- Strong knowledge in computer architecture and microarchitecture
- Good knowledge of Python, C, C++, Verilog
- Good knowledge of processor simulators (e.g. M5)
- Some knowledge of design tools (e.g. Cadence, Synopsis)