Transactions on HiPEAC: Volume 4, Issue 4

William Plishker, Nimish Sane, Mary Kiemb, and Shuvra S. Bhattacharyya Heterogeneous Design in Functional DIF,2009. [article]

Daniel Llorente, Kimon Karras, Thomas Wild and Andreas Herkersdorf Advanced Packet Segmentation and Buffering Algorithms in Network Processors,2009. [article]

Ben Cope, Peter Y.K. Cheung, Wayne Luk and Lee Howes A Systematic Design Space Exploration Approach to Customising Multi-Processor Architectures: Exemplified using Graphics Processors,2009. [article]

Valeriu Beiu, Basheer A.M. Madappuram, Peter M. Kelly, and Liam J. McDaid On Two-layer Brain-inspired Hierarchical Topologies – A Rent’s Rule Approach –,2009. [article]

Stanley Jaddoe, Mark Thompson, and Andy D. Pimentel Signature-based Calibration of Analytical Performance Models for System-level Design Space Exploration,2009. [article]

Markus Rullmann and Renate Merker A Cost Model for Partial Dynamic Reconfiguration,2009. [article]

W.G. Osborne, W. Luk, J.G.F. Coutinho and O. Mencer Energy Reduction by Systematic Run-Time Reconfigurable Hardware Deactivation,2009. [article]

Yasutaka Wada, Akihiro Hayashi, Takeshi Masuura, Jun Shirako, Hirofumi Nakano, Hiroaki Shikano, Keiji Kimura, and Hironori Kasahara A Parallelizing Compiler Cooperative Heterogeneous Multicore Processor Architecture,2009. [article]

Xiongfei Liao, Wu Jigang and Thambipillai Srikanthan A Modular Simulator Framework for Network-on-Chip Based Manycore Chips Using UNISIM,2009. [article]

Mohammad Ansari, Mikel Luj´an, Christos Kotselidis, Kim Jarvis, Chris Kirkham, and Ian Watson Transaction Reordering to Reduce Aborts in Software Transactional Memory,2009. [article]

Adam Welc and Bratin Saha Software Transactional Memory Validation – Time and Space Considerations,2009. [article]