Pinhole Processing in the Multicore and Post-Multicore Eras

Dear colleague,

BSC-DAC-UPC invite you to attend online the following talk:

Title: Pinhole Processing in the Multicore and Post-Multicore Eras
Speaker: Doug Burger (Computer Architecture Group at Microsoft Research)
Date: Mon 20, 11:00 (CET)
URL: http://www.ac.upc.edu/video/index,en.html

If you would like to ask questions to the speaker, please send an e-mail to seminar@hipeac.ac.upc.edu

Best regards,

Enric Morancho

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Abstract

Power efficiency has constrained the growth of single-threaded performance, but will soon also constrain the scaling of multicore chips. In this talk, I will project how Moore's Law will affect multicore designs, and show that energy efficiency will determine the number of cores that we can fit on a chip, leading to a model that I call "pinhole processing." To address the efficiency of individual cores, I will describe the TFlex microarchitecture, a class of ultra-adaptive EDGE-based cores that can enable dynamic heterogeneity through composability, subsuming many of the heterogeneous multicore design points. Finally, I will offer some thoughts on what comes after multicore.

Bio

Doug Burger is a Principal Researcher and manager of the Computer Architecture Group at Microsoft Research. He is currently on leave from the University of Texas at Austin, where he is a Professor of Computer Sciences and Electrical & Computer Engineering, and where he co-ran the TRIPS project, which developed EDGE architectures and NUCA memory systems. His research interests are in computer architecture, power-efficient computing, novel computing technologies, and compilers. He received the ACM Maurice Wilkes Award in 2006, was named an ACM Distinguished Scientist in 2008, and is Chair of ACM SIGARCH.