Transactions on HiPEAC: Volume 3, Issue 3

Submitted by pers_1 on Mon, 15/09/2008 - 10:35

T. Saidani, L. Lacassagne, J. Falcou, C. Tadonki, Samir Bouaziz Parallelization Schemes for Memory Optimization on the Cell Processor : A Case Study on the Harris Corner Detector. Transactions on High-Performance Embedded Architectures and Compilers,2008. [article]

H. Devos, J. Van Campenhout, I. Verbauwhede, D. Stroobandt Constructing Application-specific Memory Hierarchies on FPGAs. Transactions on High-Performance Embedded Architectures and Compilers,2008. [article]

(Caution: page numbers may change in final print)