MEDEA Workshop: MEmory performance: DEaling with applications, systems and Architecture
MEDEA Workshop
Workshop on MEmory performance: DEaling with applications, systems and Architecture
http://garga.iet.unipi.it/medea08
MEDEA-2008 aims to continue the high level of interest of the previous editions held with PACT Conference since 2000.
Due to the ever-increasing gap between CPU and memory speed, there is always great interest in evaluating and proposing processor, multiprocessor, CMP, multi-core and system architectures dealing with the "memory wall" and wire-delay problems. At the same time, a modular high-level design is becoming more and more attracting in order to reduce design costs. In this scenario, design solutions and their corresponding performance are shaped by the combined pressure of a) technological opportunities and limitations, b) features and organization of system architecture and c) critical requirements of specific application domains.In particular, the emerging trend of single-chip multi-core solutions, will push towards new design principles for memory hierarchy and interconnection networks, especially when the design is aimed to build systems with a high number of cores, which aim to scale performance and power efficiency in a variety of application domains.
From a slightly different point of view, the mutual interaction between the application behavior and the system on which it executes, is responsible of the figures of merit of the memory subsystem and, therefore, pushes towards specific solutions.
Typical architectural choices of interest include, single processors, chip multiprocessors, SoC, tiled/clustered architectures, multithreaded or VLIW architectures, massive parallelism designs, heterogeneous architectures, architectures equipped with application-domain accelerators as well as endowed with reconfigurable modules. The emerging network on chip infrastructure and transactional memory may suggest new solutions and issues.
Proceedings of the Workshop will be published under ACM ISBN. As in the previous year, a selection of papers will be considered for publication on transactions on HIPEAC (http://www.hipeac.net/journal).
The format of the workshop includes the presentation of selected papers and discussion after each presentation.
Topics of Interest:
- Memory hierarchy design, analysis, tuning for embedded, general and special purpose systems
- On-chip Multiprocessors and System On Chip architectures, development tools and applications
- Issues in memory hierarchy design of scalable single chip systems
- Memory hierarchy issues for heterogeneous and accelerator-based systems
- Low-Power/Wire Delay design of memory hierarchies
- Inter-Chip and Intra-Chip memory latency tolerant and reduction techniques
- Cache coherence and memory models
- Exploitation of application parallelism (e.g.: ILP, TLP, DLP)
- Transactional Memory
- Compile/link time optimization techniques
- Network On Chip
- Academic/industrial experience in high performance, embedded systems and memory design
Information for Authors
The papers should be 6-8 pages in length. The abstracts and papers should be submitted in PDF format by email to Pierfrancesco Foglia and Sandro Bartolini.
Paper should be written in standard ACM SIG Proceedings Template.
Please email submissions by August, 7th 2008.
Authors will be notified of acceptance or rejection by September, 21st 2008 and the final papers are due by September, 28th 2008.
To speed-up the reviewing process, we encourage also submission of abstract by July 31st, 2008.
All submissions will be refereed,
and Proceedings with ACM ISBN will be printed and distributed at the workshop (They appear in ACM DL in the following weeks).
DATES
July 31, 2008 Abstract Submission (not mandatory)
August 07, 2008 Paper Submission Deadline
September 21, 2008 Notification of Acceptance
September 28, 2008 Final Papers Due
October 25-26, 2008 MEDEA-2008 Workshop held in PACT (to be defined)
Organizing and steering commettee
Sandro Bartolini, bartolini@dii.unisi.it
University of Siena, Italy
Pierfrancesco Foglia, foglia@iet.unipi.it
University of Pisa, Italy
Cosimo Antonio Prete, prete@iet.unipi.it
University of Pisa, Italy
Roberto Giorgi, giorgi@acm.org
University of Siena, Italy
Program Committee
Erik Altman, IBM T.J. Watson Research Center, NY, USA
Davide Bertozzi, Università di Ferrara, Ferrara, Italy
Alessio Bechini, Università di Pisa, Pisa, Italy
Matt. Blumrich, IBM Watson Research Center, NY, USA
Vincenzo Catania, Università di Catania, Catania, Italy
John Cavazos, University of Delaware, Newark, DE, USA
Marcelo Cintra, University of Edinburgh, Edinburgh, UK
Derek Chiou, University of Texas at Austin, TX, USA
José Flich, UPV, Valencia, Spain
Bjoern Franke, University of Edinburgh, Edinburgh, UK
Koji Inoue, Kyushu University, Fukuoka, Japan
Timothy Jones, University of Edinburgh, Edinburgh, UK
David Kaeli, Northeastern University, Boston, MA, USA
Krishna Kavi, University of North Texas, Denton, TX, USA
Changkyu Kim, Intel Corporation, Santa Clara, CA, USA
Hiroaki Kobayashi, Tohoku University, Sendai, Japan
David M. Koppelman, LSU, Baton Rouge, LA, USA
Enrico Martinelli, Università of Siena, Siena, Italy
Mike Marty, Google, Madison, WI, USA
Avi Mendelson, Intel, Haifa, Israel
Alex. Milencovich, Un. of Alabama, Huntsville, AL, USA
Afrin Naz, Drake University, Des Moines, Iowa, USA
Kunle Olukotun, Stanford University, Stanford, CA, USA
Toshinori Sato, Fukuoka University, Japan
André Seznec, IRISA, Rennes Cedex, France
Cristina Silvano, Politecnico di Milano, Milano, Italy
Theo Ungerer, University of Augsburg, Germany
Mateo Valero, UPC, Barcelona, Spain
Wei Zhang, Southern Illinois Univ., Carbondale, IL, USA