Transactions on HiPEAC: Volume 3, Issue 1

Miquel Moreto, Francisco J Cazorla, Alex Ramirez, Mateo Valero Dynamic Cache Partitioning Based on the MLP of Cache Misses. Transactions on High-Performance Embedded Architectures and Compilers, 3(1):1-21, 2008. [article]

Chun-Chieh Lin, Chuen-Liang Chen Cache Sensitive Code Arrangement for Virtual Machine. Transactions on High-Performance Embedded Architectures and Compilers, 3(1):22-41, 2008. [article]

Subhradyuti Sarkar, Dean M. Tullsen Data Layout for Cache Performance on a Multithreaded Architecture. Transactions on High-Performance Embedded Architectures and Compilers, 3(1):42-68, 2008. [article]

Yiannakis Sazeides, Andreas Moustakas, Kypros Constantinidis, Marios Kleanthous Improving Branch Prediction by considering Affectors and Affectees Correlations. Transactions on High-Performance Embedded Architectures and Compilers, 3(1):69-88, 2008. [article]