Interconnects cluster roadmap

The next step in refining the HiPEAC Roadmap will be to list and categorize the major technical challenges that need to be solved in the next five or ten years and beyond. Each HiPEAC research cluster will contribute its own challenges, categorized according to the "six pillars" of figure 7 (page 51) of the HiPEAC Vision document. Below, we list the Interconnects Challenges that were identified by the members of the Interconnects Cluster in their June 2008 input (attached below) to the Roadmap process, in the proposed new categorization.

Within each category, challenges are listed in the proposed priority order, i.e. according to significance/impact. The parenthesis at the end of each challenge encodes short-term or long-term nature:

• (ST) short-term means that significant progress in solving this challenge is expected (and needed) by about 2015;
• (LT) long-term means that this is a hard challenge, expected to still attract significant research efforts during the second half of the decade, 2016 - 2020.

Please, give us your opinions on all these, by filing your comments (button on the bottom left of the page)!

A. Design Space Exploration

1. Network traffic models and benchmarks (ST)
2. Realistic performance/power models of network architecture and components (ST)
3. Unifying platforms for complete design-space exploration of the entire system, including the interconnects (from architectural concepts to circuit implementations) (LT)

B. Concurrent programming models and auto-parallelization

1. Network interface mechanisms for efficient support of interprocessor communication and/or cache coherence protocols (ST)
2. Support for multiple outstanding transactions and out-of-order completion (LT)

C. Electronic Design Automation

1. Full-system simulation with details of the interconnection network and network interfaces integrated (ST)
2. Application-specific interconnection networks and the corresponding design automation tools (from architecture description to circuit implementations) (ST)
3. Design of interconnection modules for reusability and ease of integration; interface standards (ST)
4. Network and protocols for improved system observability (LT)
5. Hardware/software primitives for design error detection and diagnosis (LT)

D. Design of optimized components

1. Switch microarchitecture, and interconnection network architecture for reducing: (a) energy-delay, (b) latency, and (c) silicon area (ST)
2. Power-performance optimized flow control and congestion management techniques (LT)
3. Memory controller integration with the on-chip network interfaces (ST)
4. Reduction of protocol conversion and packetization overhead (LT)
5. Interconnects with dynamic power management (per link or per switch methods) taking into account the time-evolving workloads (ST)
6. Distributed power management policies. Power-off or drowsy modes of operations that are decided locally and communicated globally via the network (ST)
7. Switches interfaced to processors that follow independently a dynamic voltage/frequency scaling policy to reduce their power. Effects on flow control and buffering requirements (ST)
8. Efficient management of thermal issues. Congestion/temperature analogy. Techniques that try to avoid hot areas or reduce incoming traffic to a region with high-temperature (LT)

E. Self-adaptive systems

1. Network traffic monitoring and control, for use by the runtime system (ST)
2. Robust interconnection network design and protocols in the presence of transient faults; efficient error detection and correction/recovery mechanisms (LT)
3. Adaptive runtime techniques to divide the total energy/power budget between computation and communication on a per application basis (LT)
4. Practical reconfiguration techniques (at run-time or in idle periods) of routing algorithms (LT)
5. Adaptive inter-node timing synchronization in the presence of variability (ST)
6. Flow control adaptation to tackle variable switch performance throughout the chip (LT)
7. In-network process variation monitoring (LT)

F. Virtualization

1. Interconnection network and network interface architectures involving protection, scheduling, and flow control for virtualization and quality-of-service (QoS), both on-chip and across chips (LT)
2. System Security: network-level threat detection; secure end-to-end data transfers with the synergy of new hardware primitives and software approaches (LT)
3. Energy-delay exploration of virtualization: Which approach is more effective? Physical partitioning of the network or allowing virtual logical partitions of the network to share the common physical components (switches and links)? How can topologies and routing algorithms help in system partitioning and isolation? (ST)

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Interconnects_RoadMap_Questions_Jun08.pdf	71.3 KB