HW/SW Support of a Soft Floating-point Unit on multiple soft ARM cores on a FPGA

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Description

The purpose of this internship is to explore the issues of putting a soft floating-point unit in soft multi-core system on a FPGA. Several Cortex-M1 soft ARM cores can be placed on a commercial FPGA to design a soft multi-core system. The initial phase of this internship will explore the hardware and software issues when interfacing a floating-point unit with a M1 soft core. Then, interfacing it with multiple M1s, synchronization, communication and coherence models will be investigated.

Requirements:

The candidate should be a Ph.D student, and have knowledge on processor microarchitectures, FPGAs, and good skills in Verilog.