Description:

Why this cluster ?Currently, HiPEAC funds a single engineer for both the compilation and simulation platform. During the first year, we have come to realize that the platforms can play a strong integrating role in the network, and a significant number of researchers have expressed interest and proposed to contribute to both platforms; at the review process, the Commission also seems to view favorably the efforts on the platforms. For the moment, the engineer has been mainly working on the simulation platform, and it has become obvious that this is at least a full-time task for one engineer. In order to realize both the integrating role of the platforms, and the corresponding research tasks, we believe it is really necessary to have a full-time engineer for each platform. As the implementation effort on the compilation platform is about to start, we felt the timing is right to ask for funding for another full-time engineer for the platforms. Also, for the moment, there is no funding allocated for travel related to the simulation platform (two clusters have been allocated for exploring the compilation platform alternatives). For both the engineers, and the researchers willing to participate to the simulation platform discussions, we need to request travel funding. Technically, what will be the tasks of the engineers ?SIMULATION PLATFORM. The initial study for the simulation platform has been conducted and converged to a modular interoperable environment. This platform is modular not only in the sense that a simulator is decomposed into independent blocks with clear interfaces to other blocks, but also because the control is distributed over modules thanks to a control abstraction embedded in the module ports. Combined with a public library, we expect this approach will strongly facilitate the exchange, reuse and comparison of simulation efforts and architecture ideas among researchers, including between academic and industry researchers. The platform is interoperable because, through a set of wrappers, it allows to interconnect several different existing simulation platforms, allowing academic and industrial groups to leverage their past developments while still opening up to the proposed shared platform. Beyond current European efforts, this platform has the backing of a consortium of prominent American researchers. The tasks of the engineer will be the following:

• develop a first robust version of the platform for dissemination, based on the prototype composed of bits and pieces of the existing MicroLib and Liberty platforms;
• develop several simulators for the library that will come together with the platform: at least one generic CMP simulator, a few models of company simulators (ARM, ST, possibly others);
• develop functional simulators and an API for the functional simulators that feed the timing simulators;
• participate to the development of a full-system extension to the CMP simulator, possibly other library simulators;
• develop and maintain the web site for library dissemination, submission of modules to the library, documentation of the platform, etc;
• implement hooks in modules to allow third-party tools such as power modeling, graphical user interface, simulation speedup techniques, etc;
• assist any academic or industrial research group willing to test and implement the platform at its site; the assistance includes training on the platform and stays to participate to development work; more specifically, a training session is already planned at UPC in January, as well as the harmonization of the current CMP simulation efforts conducted at Chalmers and UPC with the HiPEAC simulation platform;

COMPILATION PLATFORM. The initial study has highlighted GCC as the most appropriate compiler platform for HiPEAC. It already has a strong backing from at least two HiPEAC companies (IBM and Philips), and several academic researchers have expressed interest. GCC has been selected because it is the only open and free compiler environment which has been supported for a very long time, thus maximizing the probability that research efforts over the duration of the network will have a lasting effect on the community. Moreover, it leverages the contributions of a striving community, which recently has been receiving increased and significant backing from companies. The latest version of GCC, GCC 4, while still containing few optimizations yet, has a new structure which should enable the easy addition of stateof-the-art optimization, as well as research exploration. The proposed approach for using GCC as the HiPEAC compiler research platform is to create and maintain a HiPEAC branch of GCC, in order to both keep in sync with the main GCC developments (by synchronizing the branch with the official release) and to allow the fast adoption/implementation of research ideas (because the branch would be driven by HiPEAC). The main tasks of the engineer will be the following:

• maintain and synchronize the HiPEAC branch of GCC (we expect this task to be especially time-consuming as GCC progresses at a rapid pace);
• conversely, attempt to disseminate elements of the HiPEAC branch to the wider GCC community and the official GCC release;
• progressively implement a rich set of optimizations in GCC, to support, among other, research approaches such as iterative optimization;
• provide training and support for research groups willing to move to GCC;

WhoBeyond the institutions leading the simulation and compilation platform (Chalmers, University of Edinburgh), this proposal is supported by INRIA which is playing an active role in both platforms, IBM and Philips which actively participate in the GCC compilation platform, ST which expressed interest in the GCC compilation platform, ARM which expressed interest in the simulation platform, and by UPC which expressed interest as a potential test user for both platforms as well, and to lead the development for full-system simulation (though this part may require a whole separate cluster). University of Cantabria is also willing to bring its multiprocessor expertise to the simulation platform. Ghent University is willing to participate for the simulation speed issues.

Nature:
Research cluster

Total funding:
Requested: € 67600
Granted: € 67600

Including fellowship funding:
Requested: € 60000
Granted: € 60000

Description of how the funding will be used:

ENGINEER. Funding is requested for a full-time engineer (one being already part of the HiPEAC budget plan) and travel funding for the engineers, and for researchers participating to the platforms. Assuming we consider the current engineer (Sylvain Girbal) will be dedicated to the simulation platform (he started on that platform for a few months now), the new engineer will dedicated to the compilation platform, and by default, we assume for the moment he will be recruited at Univ. of Edinburgh. Thus, the expected and approximate yearly cost of the engineer is 60000 Euros. TRAVEL. Up to now, each platform meeting (simulation or compilation) gathered around 20 persons. However, many of these persons are already being funded, including for the compilation platform (GCC, COSY). So it is reasonable to assume around 3 persons per meeting coming exclusively for the platforms meetings and not otherwise funded; we can consider 2 out of 3 can already be covered with the existing compilation platform clusters, so overall, we need to fund 4 persons per clusters meeting for both the simulation and compilation platform. With 3 clusters meetings per year (plus the summer school, not counted), we need to fund 3x4 = 12 trips per year; for a cost of 400 Euros per trip (2-day trips), it is a total of 18*400=4800 Euros. In addition, we can expect the two engineers to travel on-site to provide training and assistance, about twice per year for each platform, i.e., 4 stays of 5 days per year in total, with an individual cost of 700 Euros per 5-day cost, i.e, 2800 Euros for the 4 stays. Overall, 7600 Euros for travel funding per year.Overall, the requested funding is 60000 (engineer) + 7600 (travel) = 67600 per year. We expect to request the same funding until the end of the network, i.e., over the next 3 years.

Duration of the funding:
Requested: 12 month(s)
Granted: 12 month(s), starting on: Tue, January 1, 1980

Participating members:
STENSTROM Per (Chalmers University of Technology) (--member--)
O'BOYLE Michael (Edinburgh University) (--member--)
MARTORELL Xavier (UPC) (--member--)
RAMIREZ Alex (UPC) (--member--)
TEMAM Olivier (INRIA) (--member--)
COHEN Albert (INRIA) (--member--)
EECKHOUT Lieven (Ghent University) (--member--)
BEIVIDE Ramon (University of Cantabria) (--member--)
BERNSTEIN David (IBM) (--member--)
MENDELSON Bilha (IBM) (--member--)
ZAKS Ayal (IBM) (--member--)
DURANTON Marc (NXP) (--member--)
CORNERO Marco (STMicroelectronics) (--member--)
FLAUTNER Krisztian (ARM) (--member--)

Other people collaborating:

• Grigori Fursin, INRIA
• Adrian Cristal, UPC
• Valentin Puente, Jose Angel Gregorio, Univ. Cantabria
• Zbigniew Chamski, Philips
• Sami Yehia, ARM