Scalable System Architectures


Building scalable systems is becoming more and more important due to

the increasing need for compute and storage resources mainly in

commercial services and applications. Such systems will be the basic

components of future datacenters and IT infrastructure in general.

Using existing, commodity components for processing, storage, and

communication to build scalable systems is an appealing approach for

cost reasons. For this reason, a lot of research has been conducted

in this area over the past years with great progress.



The arhitecture of such systems is expected to change dramatically

with the proliferation of explicit parallelism and new communication

mechanisms at all system levels: within the CPU, on-board, in-the-box,

outside-the-box. These developments present great opportunity,

however, require further research in communication and system issues

both at the architectural and run-time system level.



The goal of this Research Cluster is to deal with the architecture of

future scalable systems and to reconsider related issues in light of

new technology trends. Emphasis will be placed on subsystems and

mechanisms for communication among compute and storage components.

Research topics of particular interest and challenging open questions

include:



* Processor to Network and Storage I/O Interfaces, especially:

- Architectures for low-cost NIC's, scalable to 10-100 Gb/s and

for commodity link technologies;

- Novel types of functionality to be supported by the network

and storage I/O subsystem.



* Interconnection Networks, especially:

- On-chip interconnects and relationship to existing off-chip solutions;

- Commodity switch architectures;

- Scalable switching fabrics;

- Flow and congestion control.



* Multiprocessor Architectures at different Scales:

- On-chip multiprocessors, multi-threaded CPUs;

- Network Processors, Network-Level Parallelism;

- Chip-level, Board-level (SMP), Cluster-level parallelism.



* Novel applications, especially:

- Workload characterization for deep parallelism and multi-level

communication;

- Enabling new compute and storage applications, commercial or

scientific, with requirements that exceed today's infrastructure

capacity, e.g. content archival and delivery systems.



* Overall system architecture, especially:

- Protocols for efficient, scalable, and reliable communication,

and division of functionality between host, network interface,

and network fabric;

- Runtime system (OS and user-level) support for communication and

storage I/O;

- Server system reliability, availability, and security.



Research cluster

Requested: € 20000
Granted: € 10000

Requested: € 0
Granted: € 0

Two meetings over the next three to six months (e.g. in two of our

three locations, Spain, Sweden, Greece), to discuss and coordinate

our research and our plans. Each meeting/visit: 2-5 days.



Each meeting costs approximately:

6 cross-country trips @ approx. 1400 Euro each, plus

2 in-country trips @ approx. 800 Euro each, equals approximately

= 10000 Euro per meeting.



Next activities will likely include student exchanges/fellowships,

more meetings, etc.


Requested: 6 month(s)
Granted: 12 month(s), starting on: Fri, November 30, 1979

MARKATOS Evangelos (University of Crete) (--colleague--)
LYSNE Olav (Simula Research Laboratory) (--member--)
KATEVENIS Manolis (FORTH) (--member--)
HAGERSTEN Erik (Uppsala University) (--colleague--)
DUATO Jose (University Politecnica de Valencia) (--member--)
BILAS Angelos (FORTH) (--member--)
BIANCO Andrea (Politecnico di Torino)
BEIVIDE Ramon (University of Cantabria) (--member--)
PNEVMATIKATOS Dionisios (FORTH) (--member--)
BRORSSON Mats (Royal Institute of Technology) (--colleague--)
NAVARRO Nacho (UPC) (--member--)

IBM Zurich recently applied to become a member of HiPEAC

and we know that they are interested on several of the

topics of this research cluster; we propose to contact them

for possible collaboration.