User login |
Reconfigurable computing (extension)Reconfigurable Computing This cluster is extension of clusters 457 and 994 “Reconfigurable Computing”. The main intention continues to be involving all top researchers in Europe in the area of reconfigurable computing. For example, after attending our cluster meetings, Juergen Teich (University of Erlangen-Nuremberg, Germany) applied and was accepted as HiPEAC member. We also have continued conversations with several relevant companies to join HiPEAC. For example, Robert Esser, Director of Xilinx Research Labs Ireland is seriously considering membership in HiPEAC2. We are currently organizing the second “Workshop on Reconfigurable Computing” to be held in conjunction with the HiPEAC 2008 Conference in Sweden. The keynote presentation is by Wayne Luk (Imperial College London) who got involved with HiPEAC via this cluster. There is growing interest in this workshop from the reconfigurable computing research community and we expect much higher number of submissions (at least the double) compared to last year. We have continued publishing work done in the cluster in high quality Journals (some examples): - Ioannis Sourdis, Dionisios Pnevmatikatos, Stamatis Vassiliadis, Scalable Multi-Gigabit Pattern Matching for Packet Inspection, to appear in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Special Section on Configurable Computing Design, 2007/2008. - Ioannis Sourdis, Joao Bispo, Joao M.P. Cardoso and Stamatis Vassiliadis, Regular Expression Matching in Reconfigurable Hardware, to appear in Int. Journal on VLSI and Signal Processing (Springer), 2007. - S. Vassiliadis, I. Sourdis, FLUX Interconnection Networks on Demand, Journal of Systems Architecture, pp. 777-793, October 2007, vol. 53 (10) Elsevier - E. Moscu Panainte, K.L.M. Bertels, S. Vassiliadis, The Molen Compiler for Reconfigurable Processors, ACM Transactions in Embedded Computing Systems (TECS), February 2007, Volume 6, Issue 1 - S. Fekete, J. van der Veen, A. Ahmadinia, D. Göhringer, M. Majer and J. Teich. Offline and Online Aspects of Defragmenting the Module Layout of a Partially Reconfigurable Device. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, accepted, September 2007. - Ricardo Chaves, Georgi Kuzmanov, Leonel Sousa, Stamatis Vassiliadis, Cost-Efficient SHA Hardware Accelerators, to appear in IEEE Transactions on Very Large Scale Integration Systems (TVLSI). Also top conferences remained the primary target for this cluster: - C. Kachris, S. Vassiliadis, A Reconfigurable Platform for Multi-Service Edge Routers, Proceedings of the 20th ACM Symposium on Integrated Circuits and Systems Design, Rio de Janeiro, Brazil, September 2007. - F. J. Bouwens, M. Berekovic, A. Kanstein, G. N. Gaydadjiev, Architectural Exploration of the ADRES Coarse-Grained Reconfigurable Array, proceedings of Int. Workshop on Applied Reconfigurable Computing (ARC 2007), pp. 1-13, Rio de Janiero, Brazil, March 2007, LNCS 4419 - C.H. Ho, C.W. Yu, P.H.W. Leong, W. Luk, S.J.E. Wilton “Domain-Specific FPGA: Architecture and Floating Point Applications”, Field Programmable Logic, 2007 (Awarded best paper). - J.Y. Hur, S. Wong, S. Vassiliadis, Partially Reconfigurable Point-to-Point Interconnects in Virtex-II Pro FPGAs, Proceedings of international workshop on applied reconfigurable computing (ARC07), In LNCS 4419, pp. 49-60, Rio de Janeiro, March 2007 - J. C. Bispo, I. Sourdis, J. M.P. Cardoso, S. Vassiliadis, Synthesis of Regular Expressions Targeting FPGAs: Current Status and Open Issues, Int. Workshop on Applied Reconfigurable Computing (ARC 2007), pp. 179-190, Mangaratiba, Rio de Janiero, Brazil, March 2007, LNCS - C. Kachris, C. Kulkarni, Configurable Transactional Memory, Proceedings of 15th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 07), Napa, CA, USA, April 2007 - Y. D. Yankova, K.L.M. Bertels, S. Vassiliadis, R. J. Meeuws, A.J.R. Virginia, Automated HDL Generation: Comparative Evaluation, Proceedings of International Symposium on Circuits and Systems (ISCAS2007), pp. 2750-2753, New Orleans, USA, May 2007 - J.Y. Hur, T. Stefanov, S. Wong, S. Vassiliadis, Customizing Reconfigurable On-Chip Crossbar Scheduler, IEEE 18th International Conference on Application-specific Systems, Architectures and Processors (ASAP07), Montreal, Canada, July 2007 - C. Kachris, S. Vassiliadis, Design Space Exploration of Configuration Manager for Network Processing Applications, Proceedings of IEEE International Symposium on Systems, Architectures, Modeling and Simulation (SAMOS 07), Samos, Greece, July 2007 - S.J. Raaijmakers, S. Wong, Run-Time Partial Reconfiguration for Removal, Placement and Routing on the Virtex-II Pro, Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL07), Amsterdam, The Netherlands, August 2007 - S. Vassiliadis, F. Duarte, S. Wong, A Load/Store Unit for a memcpy Hardware Accelerator, Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL07), pp. 537--541, Amsterdam, The Netherlands, August 2007 - SD Breijer, F. Duarte, S. Wong, An OCM Based Shared Memory Controller For Virtex 4, Proceedings of 17th International Conference on Field Programmable Logic and Applications (FPL07), pp. 692--696, Amsterdam, The Netherlands, August 2007 -Y. D. Yankova, G.K. Kuzmanov, K.L.M. Bertels, G. N. Gaydadjiev, J. Lu, S. Vassiliadis, DWARV: DelftWorkbench Automated Reconfigurable VHDL Generator, In Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL07), pp. 697-701, Amsterdam, The Netherlands, August 2007 - R. J. Meeuws, Y. D. Yankova, K.L.M. Bertels, G. N. Gaydadjiev, S. Vassiliadis, A Quantitative Prediction Model for Hardware/Software Partitioning, Proceedings of 17th International Conference on Field Programmable Logic and Applications (FPL/07), pp. 5, Amsterdam, The Netherlands, August 2007 - C. Kachris, S. Vassiliadis, A Reconfigurable Platform for Multi-Service Edge Routers, Proceedings of the 20th ACM Symposium on Integrated Circuits and Systems Design, Rio de Janeiro, Brazil, September 2007 - A. Kupriyanov, D. Kissler, F. Hannig and J. Teich. Efficient Event-driven Simulation of Parallel Processor Architectures. In Proceedings of the 10th International Workshop on Software and Compilers for Embedded Systems (SCOPES), Nice, France, April 20, 2007. - D. Koch, C. Haubelt and J. Teich, Efficient Hardware Checkpointing -- Concepts, Overhead Analysis, and Implementation. In Proceedings of the 15th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2007), Monterey, CA, February 18-20, 2007. - John Kelm, Isaac Gelado, Mark Murphy, Nacho Navarro, Steve Lumetta and Wen-mei Hwu, "CIGAR: Application Partitioning for a CPU/Coprocessor Architecture" Parallel Archittectures and Compilation Techniques (PACT'07), Sep. 2007. - Rui Rodrigues, Joao M. P. Cardoso, and Pedro C. Diniz, "A Data-Driven Approach for Pipelining Sequences of Data-Dependent Loops," in 15th Annual IEEE Symposium on Field Programmable Custom Computing Machines (FCCM'07), Napa Valley, CA, USA, April 23 - April 25, 2007, IEEE Computer Society Press. - Carlos Morra, Joao M. P. Cardoso, and Juergen Becker, "Using Rewriting Logic to Match Patterns of Instructions from a Compiler Intermediate Form to Coarse-Grained Processing Elements," in 14th Reconfigurable Architectures Workshop (RAW'07), IEEE International Parallel and Distributed Processing Symposium, (IPDPS'2007), Long Beach, California, USA, March 27 - 28, 2007, IEEE Computer Society Press, pp. 1-8. - J. Tao, A. Shahbahrami, B. Juurlink, R. Buchty, W. Karl, S. Vassiliadis: Optimizing Cache Performance of the Discrete Wavelet Transform Using a Visualization Tool, The 2007 IEEE International Symposium on Multimedia (ISM-07), Taichung, Taiwan, December 10-12, 2007 - R. Buchty, F. Nowak, W. Karl, A Run-time Reconfigurable Cache Architecture, ParaFPGA: Parallel Computing with FPGAs as part of the Parallel Computing Conference 2007 (ParCo 2007), Jülich, September 4-7, 2007 1. General Introduction: The proposition of the cluster is that reconfigurable processors, i.e. processors that adapt (dynamically or statically) their microarchitecture to fit application "design requirements", are the correct answer to the design challenges for processors (embedded or not) in the future. To prove the viability of the above proposition, we are working on multiple design aspects of (single and multi) processors on a chip using reconfigurable fabrics. In addition, aspects like compiler transformations and linker optimizations for hybrid software/hardware platforms, automatic synthesis of hardware accelerators, operating systems and loaders support, automated design tools and the reliability provisions of such systems are part of the intended research. 2. Cluster Organization: In this cluster we address the entire field of reconfigurable computing and coordinate the activities by several focused initiatives, rather than considering isolated topics only. This proposal covers a period of 12 months. It is intended to promote many new initiatives on the subject. The ones identified so far are as follows: o Continue to organize the annual workshop; o Consolidate research platform and tools based on existing ones; o Promote researcher exchange among the partners; o Build the critical mass needed for the successful future of RC in Europe; o Involve European industry; o Collaborate with related NSF projects (IMPACT at UIUC and ROCCC at UC-Riverside); o Maintain high quality web page to disseminate the cluster results (http://ce.et.tudelft.nl/HiPEACRC/). In addition, we are implementing common platform composed of the following parts and addressed by the full time researcher granted in 994: o Common compiler, software infrastructure (benchmarks, simulation, OS and more); o Common prototype hardware; o Common design tools suite; o Webpage about the platform and online tools. The MOLEN prototype is considered as a good candidate and the Delft workbench is a potential common compiler. 3. Cluster research topics: The topics of particular interest of this cluster are (but not limited to): 1. Technological issues: Run-time dynamic reconfiguration, reduced Power consumption; 2. Dedicated compilers and tools; 3. Application domain specific: multimedia, networking; 4. Operating System support for Reconfigurable Systems 5. Adaptive Bio-inspired reconfigurable computing; 6. Reliability, defect and fault tolerance in reconfigurable technologies; 7. System level design and HW/SW co-design for RC. Research cluster Requested: € 90000 Granted: € 60000 Requested: € 0 Granted: € 0 The funding for this cluster in this period will be mainly dedicated to cluster meetings. These meetings will be used for establishing new researcher collaborations in order to tighten the collaboration under the topic in HiPEAC1 and HiPEAC2. In addition, we will coordinate the cluster efforts, fine tune the strategy and steer the future directions during these regular meetings. The cluster budget is: -o Overall traveling budget (considering the overlap with HiPEAC2 in 2008): 3 meeting trips x Belgium 1 people Cyprus 2 people Germany 4 people Greece 2 people Netherlands 2 people Portugal 2 people Spain 2 people Sweden 2 people UK 3 people Total 20 people (3 visits each) x 1500 euro/trip = 90,000 euros Requested: 12 month(s) Granted: 0 month(s), starting on: Thu, September 27, 2007 BRUGUERA Javier D. (University of Santiago de Compostela) (--member--) EVRIPIDOU Paraskevas (University of Cyprus) (--member--) GAYDADJIEV Georgi (Delft University of Technology) (--member--) HANNIG Frank (University of Erlangen-Nuremberg) (--colleague--) KARL Wolfgang (University of Karlsruhe) (--member--) KAXIRAS Stefanos (University of Patras) (--member--) KELLY Paul (Imperial College London) (--member--) NAVARRO Nacho (UPC) (--member--) PNEVMATIKATOS Dionisios (FORTH) (--member--) STENSTROM Per (Chalmers University of Technology) (--member--) STROOBANDT Dirk (Ghent University) (--member--) TEICH Jürgen (University of Erlangen-Nuremberg) (--member--) TRANCOSO Pedro (University of Cyprus) (--member--) UNGERER Theo (University of Augsburg) (--member--) SVENSSON Lars (Chalmers University of Technology) (--member--) SOURDIS Ioannis (Delft University of Technology) (--phd student--) Joao Cardoso (INESC-ID, Portugal) Peter Cheung (Imperial college, UK) Wayne Luk (Imperial college, UK) Leonel Sousa (INESC-ID, Portugal)
|