The on-chip integration of the memory controller opens up new opportunities. Modern SoC like the Sun T2 include several processor cores together with specialized engines like the 10Gig ethernet and encryption coprocessors. In such diverse architecture, not only each core can generate a different memory pattern but also the specialized engines have different access patterns. Knowledge about the access patterns can be exposed to the memory controller. Mechanisms such as data prefetching can profit from this fact. Additionally, the high compute density also has thermal implications, because of the actitivity over the chip area devoted to the memory controller.

Our focus is on optimization mechanisms inside the memory controller considering different data streams, coming either from prefetching mechanisms or from heterogeneous cores. Thermal implications will be also considered. Previous experience on data cache design and hardware prefetching from our group (gaZ) in Zaragoza will be used to adapt and apply the SESC and SCOORE simulation platforms of Prof. Renau's group at the Univ. of California at Santa Cruz.

This funding will cover two stayings of one month each at Santa Cruz for José Luis Briz. The first staying could be scheduled for February - March, and the second along the summer, on account of J. L. Briz academic duties, and in any event before the end of Septembre 2008. As an estimate, a return ticket (Madrid - San Francisco, USA) costs 1100 EU and the hotel plus allowances plus other expenses per day at Santa Cruz is 120 EU. This adds up to:

Flights: (2 x 1100): 2200 €
Hotel plus allowances: 60 x 120 EU = 7200 €
Total: 9400 €

Enrique Torres Moreno (gaZ, Univ. Zaragoza)

At the UC Santa Clara part, there are two people involved whose activities are founded with outside financing:

José Renau (researcher)
Carlos Andres Cabrera (PhD student and Sun Microsystems Engineer)