Modular & Transaction-Level Full-System Multi-Processor Simulation

Description:

Industry and academia are fast moving from one processor per chip to Chip Multi Processors (CMP). CMPs impose three new requirements on simulation. (1) First, the operating system plays a bigger role in the management of threads, communications, etc, and therefore it must be considered in the performance evaluation process. (2) Second, standard simulators are already slow but CMP simulators can become exceedingly slow as the number of processors increases. (3) Third, communications have a bigger impact on performance than the internal operations of processors so that transaction-level modelling of CMPs can already bring a wealth of performance information.
Point (1) imposes that the simulator is capable of running the operating system and not only user-level applications, and that the full system architecture must now be modelled (MMU, peripherals, etc). Points (2) and (3) suggest that performance evaluation departs from the traditional cycle-level evaluation common in micro-architecture research and moves towards transaction-level evaluation, at least on a first step. Already, industry is using a progressive evaluation approach for such systems: first transaction level simulators, then hybrid transaction-level/cycle-level simulators to narrow in on the effect of certain architecture parts, and finally full cycle-level simulators for validation purposes.

Currently, the UniSim framework is focused on traditional cycle-level modelling and user-level processes. The purpose of this proposal is to retain the assets of UniSim (modularity, reuse, distributed control, library) and extend them to transaction/system-level modelling.

Why current full-system simulation environments are not appropriate ?

We have been evaluating the different available full-system environments for several months now. We concluded that they split in two categories. Either commercial but fairly closed systems such as Simics, which do not lend well to any internal modification; the workarounds developed for Gems, for instance, are a testimony to the lack of flexibility of the tool. Or public tools which either target only one or a few architectures/ISAs, e.g., Gems targets Sparc, M5 targets Alpha, or tools which are not designed for performance evaluation purposes, e.g., Bochs or QEmu, etc. Other tools, such as SimOS, might be more appropriate but are no longer supported. Moreover, none of these tools are designed for modularity and reuse of their individual components.

What work is needed exactly ?
• To support a full operating system. Our goal is to be able to boot Linux and/or more simple real-time operating systems from the simulator. Our first target will be a PowerPC750 booting Linux.
• To simulate a full system architecture. For that purpose, we need to implement a number of peripherals, e.g., flash and/or hard drive storage, in addition to the usual CMP components.
• To create a transaction-level protocol, built upon industry standards (SystemC TLM), that retains the benefits of distributed control as in the cycle-level UniSim protocol, but with a much faster communication process.
• To create hybrid cycle-level/transaction-level simulators. That interaction will enable progressive evaluation of increasingly detailed performance phenomena, and to leverage all the work already done for cycle-level UniSim models.

The outcome of the cluster is a full-system simulator capable of evaluating a large range of CMPs, and moreover, the corresponding system-level modules will be added to the UniSim library.

Who is involved ?

CEA is developing a PowerPC750 full-system simulator capable of booting Linux, following a user-level version developed at INRIA. INRIA is working with CEA to develop hybrid cycle-level/transaction-level simulators. UPC is developing the peripherals of the full system as well as the bus architecture.

Nature:
Research cluster

Total funding:
Requested: € 25020
Granted: € 7020

Including fellowship funding:
Requested: € 18
Granted: € 0

Description of how the funding will be used:

Description of how the funding will be used