European Network of Excellence on High Performance and Embedded Architecture and Compilation
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Transactions on HiPEAC: Volume 2, Issue 2
W. Choi,
S-J Park,
M. Dubois,
Accurate Instruction Prescheduling in
Dynamically Scheduled Processors.
Transactions on High-Performance Embedded Architectures and Compilers, 2(2):1-18, 2007.
[article]
H. Vandierendonck,
A. Seznec,
Fetch Gating Control through Speculative Instruction Window Weighting.
Transactions on High-Performance Embedded Architectures and Compilers, 2(2):19-39, 2007.
[article]
M. Ahn,
Y. Paek,
Fast Code Generation for Embedded Processors with Aliased Heterogeneous Registers.
Transactions on High-Performance Embedded Architectures and Compilers, 2(2):40-59, 2007.
[article]
D. Chanet,
J. Cabezas,
E. Morancho,
N. Navarro,
K. De Bosschere,
Linux Kernel Compaction through Cold Code Swapping.
Transactions on High-Performance Embedded Architectures and Compilers, 2(2):60-88, 2007.
[article]
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