Introduction to Part 1 by Per Stenstrom and David Whalley [article]

G. Keramidas, P. Xekalakis, S. Kaxiras, Recruiting Decay for Dynamic Power Reduction in Set-Associative Caches. Transactions on High-Performance Embedded Architectures and Compilers, 2(1):2-20, 2007. [article]

V. Nagarajan, R. Gupta, A. Krishnaswamy, Compiler-Assisted Memory Encryption for Embedded Processors. Transactions on High-Performance Embedded Architectures and Compilers, 2(1):21-41, 2007. [article]

S. Kluyskens, L. Eeckhout, Branch Predictor Warmup for Sampled Simulation through Branch History Matching. Transactions on High-Performance Embedded Architectures and Compilers, 2(1):42-61, 2007. [article]

M. Bhadauria, S. A. McKee, K. Singh, G.S. Tyson, Data Cache Techniques to Save Power and Deliver High Performance in Embedded Systems. Transactions on High-Performance Embedded Architectures and Compilers, 2(1):62-81, 2007. [article]

C. Hu, D.A. Jimenez, U. Kremer, Combining Edge Vector and Event Counter for Time-dependent Power Behavior Characterization. Transactions on High-Performance Embedded Architectures and Compilers, 2(1):82-101, 2007. [article]