HiPEAC European Network of Excellence on High Performance and Embedded Architecture and Compilation

Transactions on High-Performance Embedded Architectures and Compilers (Transactions on HiPEAC)

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Transactions on HiPEAC: Volume 1
Transactions on HiPEAC: Volume 2
Transactions on HiPEAC: Volume 3
Transactions on HiPEAC: Volume 4, Issue 1
Transactions on HiPEAC: Volume 4, Issue 2
Transactions on HiPEAC: Volume 4, Issue 3
Transactions on HiPEAC: Volume 4, Issue 4
Transactions on HiPEAC: Volume 5, Issue 1
Transactions on HiPEAC: Volume 5, Issue 2
Transactions on HiPEAC: Volume 5, Issue 3
Transactions on HiPEAC: Volume 5, Issue 4

 

Flyer: HiPEAC Journal

Scope

 
HiPEAC is a new journal which aims at timely dissemination of research contributions in computer architecture and compilation methods for high-performance embedded computer systems. Recognizing the convergence of embedded and general-purpose computer systems, this journal publishes original research on systems targeted at specific computing tasks as well as systems with broad application bases. The scope of the journal therefore covers all aspects of computer architecture and code generation and compiler optimization methods of interest to researchers and practitioners designing future embedded systems. Examples of topics of interest include:

  • Processor architectures
  • Memory system optimization
  • Power, performance and implementation effective designs
  • Network Processors
  • Security Processors
  • Application specific processors and accelerators
  • Reconfigurable architectures
  • Simulation and methodology
  • Compiler techniques
  • Feedback-directed optimization
  • Program characterization and analysis techniques
  • Dynamic compilation, adaptive execution, and continuous profiling/optimization
  • Back-end code generation
  • Binary translation/optimization
  • Code size/memory footprint optimizations
  • Interconnection networks, networks-on-chip, network interfaces and processors
  • Security, dependability, and predictability impact on architectures and compilers

Issues

The journal will have four issues per year of which about half of them focus on specific themes or topic areas – special issues. Prospective guest editors are welcome to propose themes for special issues. The journal will be very strict about handling submissions in a timely fashion.  The time to the first response will not exceed ten weeks. If only minor revisions are requested, the goal is to publish such papers within six months. Articles that are requested to undergo a major revision will be requested to be resubmitted within three months. Articles that are accepted will immediately be available electronically.

The journal will be published by Springer Verlag in their LNCS series. Each issue will appear electronically immediately on this site and via Springer’s digital library. It will also be available as a hard copy.

 


 

Editorial board

The review process is managed by an editorial board of leading experts in the areas covered by the journal. The following set of people constitutes the initial editorial board:

 
Per Stenstrom (pers at chalmers dot se), Chalmers University of Technology

Editor-in-Chief

  • Koen De Bosschere, Ghent University, Belgium
  • Michael O'Boyle, University of Edinburgh, U.K.
  • Jose Duato, UPV, Spain
  • Manolis KatevenisFORTH, Greece
  • Antonio Prete, University of Pisa, Italy
  • Andre Seznec, IRISA, France
  • Olivier Temam, INRIA, France
  • Theo Ungerer, University of Augsburg, Germany
  • Mateo Valero, UPC, Spain
  • Stamatis Vassiliadis, TU Delft, Netherlands