HiPEAC 2008: Program
Program for HiPEAC 2008
MONDAY, January 28, 2008
| 8:45 - 9:00 | OPENING |
|---|---|
| 9:00 - 10:00 | KEYNOTE. Supercomputing for the Future, Supercomputing from the Past |
| 10:00 - 10:30 | COFFEE BREAK |
| 10:30 - 12:00 |
SESSION I. Multithreaded and Multicore Processors CHAIR: Georgi Gaydadjiev, T. U. Delft, Netherlands |
| MIPS MT: A Multithreaded RISC Architecture for Embedded and Real-Time Processing | |
| rMPI: Message Passing on Multicore Processors with On-Chip Interconnect | |
| Modeling Multigrain Parallelism on Heterogeneous Multi-core Processors: A Case Study of the Cell BE | |
| 12:00-13:30 | LUNCH |
| 13:30 - 15:00 | SESSION IIa. Reconfigurable - ASIP CHAIR: Chris Gniady, University of Arizona, USA |
| BRAM-LUT tradeoff on a Polymorphic DES Design | |
| Architecture Enhancements For The ADRES Coarse-Grained Reconfigurable Array | |
| Implementation of an UWB Impulse-Radio Acquisition and Despreading Algorithm on a Low Power ASIP | |
| 13:30 - 15:00 | SESSION IIb. Compiler Optimizations CHAIR: Koen De Bosschere, University of Ghent, Belgium |
| Fast Bounds Checking Using Debug Register | |
| Studying Compiler Optimizations on Superscalar Processors through Interval Analysis | |
| An Experimental Environment Validating the Suitability of CLI as an Effective Deployment Format for Embedded Systems | |
| 15:00 - 15:30 | COFFEE BREAK |
| 15:30 - 17:00 |
SESSION III. Industrial Processors & Application Parallelization CHAIR: Mike O'Boyle, Edinburgh University, UK |
| Compilation Strategies for Reducing Code Size on a VLIW Processor with Variable Length Instructions | |
| Experiences with Parallelizing a Bio-Informatics Program on the Cell BE | |
| Drug Design Issues on the Cell BE | |
| 17:00 - 18:00 | HiPEAC Internships meeting |
Tuesday, January 29, 2008
| 8:30 - 10:00 |
SESSION IV. Power-Aware Techniques CHAIR: Mats Brorsson, KTH, Sweden |
|---|---|
| COFFEE: COmpiler Framework For Energy-aware Exploration | |
| Integrated CPU and Cache Power Management in Multiple Clock Domain Processors | |
| Variation-Aware Software Techniques for Cache Leakage Reduction using Value-Dependence of SRAM Leakage due to Within-Die Process Variation | |
| 10:00 - 10:30 | COFFEE BREAK |
| 10:30 - 12:00 |
SESSION V. High-Performance Processors CHAIR: Kevin Kissell, MIPS Technolgies Inc., France |
| The Significance of Affectors and Affectees Correlations for Branch Prediction | |
| Turbo-ROB: A Low-Cost, Simple Checkpoint/Restore Accelerator | |
| LPA: A First Approach to the Loop Processor Architecture | |
| 12:00-13:30 | LUNCH |
| 13:30 - 15:00 | SESSION VI. Profiles: Collection and Analysis CHAIR: Dimitrios Nikolopoulos, FORTH, Crete, Greece |
| Complementing Missing and Inaccurate Profiling using a Minimum Cost Circulation Algorithm | |
| Using Dynamic Binary Instrumentation to Generate Multi-Platform SimPoints: Methodology and Accuracy | |
| Phase Complexity Surfaces: Characterizing Time-Varying Program Behavior | |
| 15:00 - 15:30 | COFFEE BREAK |
| 15:30 - 17:30 |
SESSION VII. Optimizing Memory Performance CHAIR: Andreas Moshovos, University of Toronto, Canada |
| MLP-Aware Dynamic Cache Partitioning | |
| Compiler Techniques for Reducing Data Cache Miss Rate on a Multithreaded Architecture | |
| Code Arrangement of Embedded Java Virtual Machine for NAND Flash Memory | |
| Aggressive Function Inlining: Preventing Loop Blockings in the Instruction Cache |
