HiPEAC 2008: Home
The embedded market evolves rapidly, expanding the capabilities of each new device, and making the previous ones obsolete as technology advances. In order to achieve the high performance required by new embedded applications, these embedded processors are increasingly highperformance processors, with an increasing overlap between generalpurpose and embedded processors. However, performance does not simply increase with technology advances, it is essential to find a way to translate technology into performance, and such is the role of the computer architect and compiler builder.
The HiPEAC conference provides a high-quality forum for computer architects and compiler builders working in the field of high performance computer architecture and compilation for embedded systems, but is also open to general-purpose research which is becoming increasingly relevant to the embedded domain. The conference aims at the dissemination of advanced scientific knowledge and the promotion of international contacts among scientists from academia and industry. Topics of interest include, but are not limited to:
- Processor architectures
- Memory system optimization
- Power, performance and implementation efficient designs
- Interconnection networks, networks-on-chip, network interfaces and processors
- Security, dependability, and predictability support
- Application specific processors and accelerators
- Reconfigurable architectures
- Simulation and methodology
- Compiler techniques for embedded processors
- Feedback-directed optimization
- Program characterization and analysis techniques
- Dynamic compilation, adaptive execution, and continuous profiling/optimization
- Back-end code generation
- Binary translation/optimization
- Code size/memory footprint optimizations
Paper submission will be possible on this webpage.
HiPEAC also welcomes halfday tutorial/workshop proposals. They should be submitted directly to the workshops/tutorials chair by May 28, 2007 and notification will be given on June 15.