HiPEAC1 clusters

A Toolkit for MPSoC Architecture Evaluation and Optimization
Accurate and Complexity-Effective Coherence Predictors
Activation/Deactivation of Overiding Predictors in High Performance Processors for Increased Power-Efficiency
Adaptable Architectures for Embedded Applications
Adaptable Computers for Embedded Applications
Adaptable Computers for Embedded Applications 2
Adaptive Prediction Techniques for branching; prefetching; and coherence
Advanced Hardware Cache Monitors and Their Application to Reconfigurable Cache Architectures
Advanced Hardware Cache Monitors and Their Application to Reconfigurable Cache Architectures
Ahead of Time Analysis and Optimizations for Just In Time Compilation
Applications enabling the exploitation of heterogeneous architectures for the embedded market
Applications enabling the exploitation of heterogeneous architectures for the embedded market (extension)
Applying Self-x-techniques to Enhance Robustness of Networked Embedded Systems
Architecture-aware compiler solutions for energy issues in embedded systems.
Automatic Parallelization for Embedded Parallel Architectures
Automatic synthesis of Application Specific Instruction-set Processors
Binary translation in the context of virtualized environments
Characterization of Commercial Workloads in Chip Multiprocessor Architectures
CMPs-based network and storage I/O subsystems
CO-EXPLORATION OF EMBEDDED PROCESSOR ARCHITECTURES AND CODE TRANSFORMATIONS
Co-Synthesis of Instruction Set Extensions and Advanced Optimising Compilers for Configurable Embedded Processors
Collaboration on Multithreading processor design
Collaboration on vector processing research
Combined Hardware/Software Approach to Coherence for Embedded Chip Multiprocessors
Core Working Sets and Bypass: Towards Highly Efficient Memory Hierarchies
Efficient Exploitation of Multiple Levels of Parallelism for Video Codec Applications
Efficient microarchitectural policies under power constrains at minimal performance cost
Embedded multithreaded processors for hard and soft real-time systems
Embedded multithreaded processors for hard and soft real-time systems(2)
Exploiting debug information in Diablo
Embedded Tiled Architectures
Energy-efficient single-core processor design
Enhancing CellSs programming model: tailoring compilation flags through non-numerical applications
Exploring optimization techniques and runtime code selection mechanisms for heterogeneous systems
Interprocessor Communication Mechanisms
Exploring optimization techniques and runtime code selection mechanisms for heterogeneous systems (extended)
GCC research platform cluster
Hardware Accelerators for Biomedical Applications
Identification and Specialization of Frequent Patterns of Computations in Programs
Investigation of real-time capable embedded SMT processor techniques
Kilo-instruction Multiprocessors
Kilo-instruction Multiprocessors
Kilo-instruction Multiprocessors
Low overhead mechanism for remote processor procedure calls
Low power micro-architecture techniques based on loop instructions reuse
Machine Learning Techniques for Adaptive Optimization
Managing Caches for SMT and CMP (correct submission 2)
Modular & Transaction-Level Full-System Multi-Processor Simulation
Multicore Embedded System Architecture
Multithreaded Dataflow Architectures
NSF (Rutgers) - HiPEAC Collaboration on Cooperative Embedded Computing
NSF (Rutgers) - HiPEAC Collaboration on Cooperative Embedded Computing
NSF/IST Collaboration: Univ. of Patras & Princeton
Optimizing High Performance Loops for Embedded Processors
Optimizing the Memory Controller in a SoC
Paper presentation at HPCA (Austin, Texas)
Performance evaluation tools for heterogeneous multicore environments
Performance Model Driven Resource Management in Future Computer Systems
Presentation of ASPLOS paper
Reconfigurable Computing
Reconfigurable computing (extension)
Reliable Embedded Processors
Research on High Performance Interconnection Networks for Embedded Applications
Research on High Performance Interconnection Networks for Embedded Applications (extra funding for meetings)
RWTH Aachen contribution to compiler and simulation platforms
Scalable System Architectures
Scalable System Architectures (#3)
Scalable System Architectures: Additional Funding Application
Simulation and Compilation Platforms Cluster
Simulation Tools for On Chip SMT Multiprocessors
Specialization of Computational Patterns in Programs
Statistical Simulation of Multicomputer Systems and Analytical Performance Modeling
Statistical simulation techniques for uniprocessor and multiprocessor systems
System Level Performance/Power Evaluation of Stream Processing Embedded Systems
System-level Software Optimization (Extension)
System-level Software Optimization
The application of Transactional Memory to novel domains
The FlexSoC Approach Towards Reconfigurable Computing
Transactional Memory for High_performance Embedded Systems
Value Profiling Driven Optimisations for Embedded Processor Architectures and Applications
Multi-Core Temperature Control through Activity Migration
Value-driven Embedded Processors
Whole System Optimization
Research on High Performance Interconnection Networks for Embedded Applications (travel fellowship #1)
Research on High Performance Interconnection Networks for Embedded Applications (travel fellowship #2)
Research on High Performance Interconnection Networks for Embedded Applications (travel fellowship #3)
Research on High Performance Interconnection Networks for Embedded Applications (travel fellowship #4)
Research on High Performance Interconnection Networks for Embedded Applications (travel fellowship #5)
Scholarships for two students at IBM-Haifa
Modelling Multithreaded Processors for Embedded Real-Time Applications
Interconnect reconfigurability in FlexSoC
New techniques for low-power high-performance cache memories
Embedded system miniaturization and power autonomy
Intelligent Checkpointing for Kilo-instruction Processors
Confidence estimation and fetch gating using state-of-the-art branch predictors
Core Working Sets and Bypass (fellowship)
Fellowship for Adaptable Computers for Embedded Applications
Fellowship for S. Kavvadias (interprocessor communication mechanisms)
Hardware Accelerators for Biomedical Applications Extending Cluster
Hardware support for measurement based Worst-Case Execution Time analysis
Adaptable Computers for Embedded Applications 3
Adaptive Optimisation
PhD funding request: Hard Real-time Scheduling Techniques for Embedded Multithreaded Multi-core Processors
Power-efficient Cache technologies
Process Migration in Multi-Core Processors and its application to the Power Density Problem
Reconfigurable SoC with multithreded processor core extending cluster: Collaboration on Multithreading processor desig
CIGAR Paper presentation in PACT'07
Paper presentation at CASES (Seoul, Korea)
Paper presentation at HiPEAC (2/2)
Paper presentation at HiPEAC 2008 (1/2)
Paper presentation at HPCA-13
Paper presentation at PACT
Paper Presentation at PACT 2007
Paper presentation at PACT 2007
Ph.D. student funding for DAC 2005 trip
Presentation of an article at ISCA symposium
Presentation of HiPEAC 2008 paper
Presentation of ICS paper
Presentation of ICS paper
Presentation of ICS paper
Presentation of ICS paper -- bis
Presentation of LCTES paper
Presentation of PACT paper
Travel funding for INFOCOM
Travel funding for ISLPED 2005
Travel funding for ISLPED 2007
A run-time admission controller for multiple applications on FPGA
Adaptive data caches
Adding high performance features to a real-time capable embedded processor
Advanced Compiler Backend Integration
Architecture/Compiler Co-Exploration for Tightly Coupled Parallel Processors
Collaboration on implementing a highly parallel scalable video codec
Compiler support for Global System Optimization
Energy considerations in SMT-CMP processors(2) and OS job scheduler/architecture interaction in SMT/CMP processors(2)
Energy considerations in SMT/CMP processors(2) and OS job scheduler/architecture interaction in SMT/CMP processors(2)
Energy/Power considerations on SMT/CMP processors
Event-based simulation in UNISIM
Hardware implementation of an efficient architecture for high-radix switches.
HiPEAC Travel Grant: Polyhedral Compilation Methods for Irregular Applications and Non-Linear Optimization
Integration of Vector Engines and KILO-Instruction Processors
Interaction between the OS job scheduler and resource allocation in SMT/CMP processors
Investigating feasibility of using fast reconfigurable logic in a typical MPSoC
Knowledge exchange on vector simulation
Main memory compression in multicore and CellBE architectures
Modeling and Management of Parallelism and Cache Sharing in CMPs
Operating Systems for next generation DSPs
Optimization based on function versioning and runtime code selection mechanisms for heterogeneous systems. INRIA research visit
Optimized mapping of dynamic concurrent applications into embedded systems
Optimized mapping of dynamic concurrent applications into embedded systems
Research on hypervisors for massive multicore systems
Runtime/Compiler Interaction on Fine-grained Reconfigurable Accelerators
Scheduling issues in massive multithreading processors
Understanding and Exploiting Program Characteristics for TLS
NoC characterization and deployment in mono and multiprocessor systems
Cache implications of non-blocking thread execution in a multithreaded architecture
Performance Implications of Hard-Faults in Non-Architectural Resources (cluster extension)
Performance Implications of Hard Faults in Non-Architectural Resources
Reconfigurable Space and Time Adaptive Processing Engines for Positioning Systems
Embedded Real-Time Reconfigurable Simultaneous Multithreading Processor Design

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