Caches In the Many-Core Era

Dear colleague,

BSC-DAC-UPC invite you to attend the following talk:

Title: Caches In the Many-Core Era
Speaker: Hillery Hunter (IBM)
Date: Wed 4, 11:00 (CET)
URL: http://www.fib.upc.edu/sala-actes

If you would like to ask questions to the speaker, please send an e-mail to seminar@hipeac.ac.upc.edu

Enric Morancho

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Abstract

A key challenge in the field of computer architecture is "balanced" system
design, in which computational capability is well-adjusted to the supply of
data. In both academe and industry, computer architects are increasingly
drawing system roadmaps which predict many-fold increases in raw computational
throughput per chip -- hundreds of cores within the next three technology
generations. At the same time, CMOS technologists have been warning of the "end
of scaling," particularly for six-transistor SRAM. This is a disturbing
forecast, since easily 50% of microprocessor silicon area is commonly occupied
by SRAM caches. Reconciling these two divergent paths is the topic of this
talk.

A particularly long-standing debate has surrounded one dense, resilient,
on-chip storage alternative: embedded DRAM. This talk will shed light on the
technology causes of the infamous memory wall, provide a tutorial on the
technology behind eDRAM, and abstract use of SRAM replacements into the
system-level metrics of performance, capacity, and availability.

Bio

Hillery Hunter is a Research Staff Member in the Exploratory Systems
Architecture Department of IBM's T.J. Watson Research Center in Yorktown
Heights, NY. She is interested in cross-disciplinary research, spanning
circuits, microarchitecture, and compilers to achieve new solutions to
traditional problems. She has published in the area of embedded DRAM, and is
currently engaged with IBM server and mainframe development as DDR3-generation
end-to-end memory power lead. She received the Ph.D. degree in Electrical
Engineering from the University of Illinois, Urbana-Champaign.