HiPEAC 2010: Conference Program
Workshops & Tutorials program
Saturday January 23rd
- MORNING-ONLY EVENTS:
- AFTERNOON-ONLY EVENTS:
- FULL-DAY EVENTS:
Sunday January 24th
- MORNING-ONLY EVENTS:
- (Workshop) Interconnection Network Architectures: On-Chip, Multi-Chip (INA-OCMC)
- (Workshop) Workshop on Rapid Simulation & Performance Evaluation: Methods and Tools (RAPIDO)
- (Tutorial) Speedup-Test: Towards Statistical Methodology to Evaluate Program Speedups and their Optimisation Techniques
- (Tutorial) Adaptability: the Key for Future Embedded Systems
- AFTERNOON-ONLY EVENTS:
- (Workshop) Workshop on Statistical and Machine learning approaches to ARchitecture and compilaTion (SMART)
- (Workshop) Workshop on the Design for Reliability (DFR)
- (Tutorial) Teaching Introductory Computer Architecture and Programming: What, When, How?
- (Tutorial) Programming FPGA-Based Accelerators using ROCCC 2.0
- FULL-DAY EVENTS:
Conference Program
Mon Jan 25
9:00-9:15 Opening/
welcome
9:15-10:15 Keynote
1
Embedded System as
Datacenter
Bob Iannucci, CEO and
Co-founder, Sensaré LLC
Break
10:45 - 12:45 Session 1
Architectural Support for
Concurrency
Chair: Avi Mendelson,
Microsoft Israel
Remote
Store Programming: Mechanisms and Performance
Henry C. Hoffmann (MIT),
David Wentzlaff and Anant Agarwal (Tilera)
Low-overhead,
High-speed Multi-core Barrier Synchronization
John Sartori and Rakesh
Kumar (Univ. of Illinois)
Improving
Performance by Reducing Aborts in Hardware Transactional Memory
Mohammad Ansari, Behram
Khan, Mikel Lujan, Christos Kotselidis, Chris Kirkham, and Ian Watson (Univ.
of Manchester)
Energy
and Throughput Efficient Transactional Memory for Embedded Multicore Systems
Cesare Ferri (Brown University), Samantha Wood (Bryan Mawr
College), Tali Moreshet (Swartmore
College), Iris Bahar, and Maurice Herlihy (Brown University)
12:45 - 14:00 Lunch
14:00 - 16:00 Session 2
Compilation and Runtime
Systems
Chair: Carol Thomson Eidt,
Microsoft
Split Register Allocation:
Linear Complexity Without the Performance Penalty
Boubacar Diouf, Albert
Cohen (INRIA), Fabrice Rastello (ENS Lyon), and John Cavazos (Univ. of
Delaware)
Trace-Based Data Layout
Optimizations for Multi-Core Processors
Olga Golovanevsky, Alon
Dayan, Ayal Zaks (IBM Israel) and David Edelsohn (IBM)
Buffer sizing for
self-timed stream programs on heterogeneous distributed memory
multiprocessors
Paul Carpenter, Alex
Ramirez and Eduard Ayguade (BSC Barcelona)
Automatically tuning sparse
matrix-vector multiplication for
Alexander Monakov and Arutyun Avetisyan (Russian
Academy of Science), Anton Lokhmotov (Imperial College London)
GPU architectures
Break
16:30 - 18:30 Session 3
Reconfigurable and
Customized Architectures
Chair: Cristina Silvano,
Politecnico di Milano
Virtual
Ways: Efficient Coherence for Architecturally Visible Storage in Automatic
Instruction Set Extensions
Samuel Burri, Theo Kluter,
Philip Brisk, Edoardo Charbon and Paolo Ienne (EPFL Lausanne)
Accelerating
XML query matching through custom stack generation on FPGAs
Roger Moussalli, Mariam
Salloum, Walid Najjar, and Vassilis Tsotras (Univ. of California Riverside)
An
Application-aware Load Balancing Strategy for Network Processors
Rainer Ohlendorf, Michael
Meitinger, Thomas Wild, and Andreas Herkersdorf (TU Munich)
Memory-Aware
Application Mapping on Coarse Grain Reconfigurable Arrays
Yongjoo Kim, Jongeun Lee,
Aviral Shrivastava, Jonghee Yoon, and Yunheung Paek (Arizona State Univ.)
Tue Jan 26
8:45 - 10:00 Keynote
2
Larrabee: A Many-Core
Architecture for Visual Computing
Roger Espasa, Principal
Engineer, Intel
Break
10:30 - 12:30 Session 4
Multicore Efficiency,
Reliability and Power
Chair: Thomas Gross, ETH
Zuerich
Maestro:
Orchestrating Lifetime Reliability in Chip Multiprocessors
Shuguang Feng, Shantanu
Gupta, Amin Ansari, and Scott Mahlke (Univ. of Michigan)
Combining
Locality Analysis with Online Proactive Job Co-Scheduling in Chip
Yunlian Jiang, Kai Tian,
and Xipeng Shen (College of William and Mary)
RELOCATE:
Register File Local Access Pattern Redistribution Mechanism for Power and
Thermal Management in Out-of-Order Embedded Processors
Houman Homayoun, Aseem
Gupta, Alex Veidenbaum, and Fadi Kurdahi (Univ. of California Irvine)
Performance
and Power Aware CMP Thread Allocation Modeling
Yaniv Ben-Itzhak, Israel
Cidon, and Avinoam Kolodny (Technion Israel)
12:30 - 13:30 Lunch
13:30 - 14:30 Panel
"Heterogenous vs.
Homogenous Computing"
Yale Patt (UT Austin),
Roger Espasa (Intel), Hank Hoffmann (Tilera/MIT), Walid Najjar (UC Riverside)
Moderator:
Paolo Faraboschi, HP Labs
14:30 - 17:30 Guided Pisa Tour
19:00 Banquet
Wed Jan 27
8:30 - 10:30 Session 5
Memory Organization and
Optimization
Chair: Jim Dehnert, Google
Multi-Level
Hardware Prefetching using Low Complexity Delta Correlating Prediction Tables
with Partial Matching
Marius Grannaes, Magnus
Jahre and Lasse Natvig (Norwegian Institute of Science and Technology)
Scalable
Shared Cache Management by Containing Thrashing Workloads
Yuejian Xie and Gabriel H.
Loh (Georgia Tech)
SRP:
Symbiotic Resource Partitioning of the Memory Hierarchy in CMPs
Shekhar S. Srikantaiah and
Mahmut T. Kandemir (Penn State University)
DIEF:
An Accurate Interference Feedback Mechanism for Chip Multiprocessor Memory
Systems
Magnus Jahre, Marius
Grannaes and Lasse Natvig (Norwegian Institute of Science and Technology)
Break
11:00 - 13:00 Session 6
Programming and Analysis of
Accelerators
Chair: Albert Cohen, INRIA
Tagged
Procedure Calls (TPC ): Efficient runtime support for task-based parallelism
on the Cell Processor
George Tzenakis,
Konstantinos Kapelonis, Michail Alvanos, Konstantinos Koukos, Dimitrios
Nikolopoulos, and Angelos Bilas (FORTH, Greece)
Analysis
of Task Offloading for Accelerators
Roger Ferrer, Vicen Beltran
(BSC Barcelona), Marc Gonzalez, Xavier Martorell (UPC Barcelona), and Eduard
Ayguade (BSC Barcelona)
Offload
-- Automating code
Pete Cooper, Uwe Dolinsky (Codeplay), Alastair
F. Donaldson (Oxford Univ.), Andrew Richards, Colin Riley, and George Russell
(Codeplay)
migration
to heterogeneous multicore systems
Computer
Generation of Efficient Software Viterbi Decoders
Frederic de Mesmay,
Srinivas Chellappa, Franz Franchetti, and Markus Pschel (Carnegie Mellon
Univ.)
13:00 - 13:15 Closing/
awards
- (Workshop) Interconnection Network Architectures: On-Chip, Multi-Chip (INA-OCMC)
- (Workshop) Workshop on Rapid Simulation & Performance Evaluation: Methods and Tools (RAPIDO)
- (Tutorial) Speedup-Test: Towards Statistical Methodology to Evaluate Program Speedups and their Optimisation Techniques
- (Tutorial) Adaptability: the Key for Future Embedded Systems
- (Workshop) Workshop on Statistical and Machine learning approaches to ARchitecture and compilaTion (SMART)
- (Workshop) Workshop on the Design for Reliability (DFR)
- (Tutorial) Teaching Introductory Computer Architecture and Programming: What, When, How?
- (Tutorial) Programming FPGA-Based Accelerators using ROCCC 2.0
| Mon Jan 25 | ||
| 9:00-9:15 Opening/ welcome | ||
| 9:15-10:15 Keynote 1 | Embedded System as Datacenter | Bob Iannucci, CEO and Co-founder, Sensaré LLC |
| Break | ||
| 10:45 - 12:45 Session 1 | Architectural Support for Concurrency | Chair: Avi Mendelson, Microsoft Israel |
| Remote Store Programming: Mechanisms and Performance | Henry C. Hoffmann (MIT), David Wentzlaff and Anant Agarwal (Tilera) | |
| Low-overhead, High-speed Multi-core Barrier Synchronization | John Sartori and Rakesh Kumar (Univ. of Illinois) | |
| Improving Performance by Reducing Aborts in Hardware Transactional Memory | Mohammad Ansari, Behram Khan, Mikel Lujan, Christos Kotselidis, Chris Kirkham, and Ian Watson (Univ. of Manchester) | |
| Energy and Throughput Efficient Transactional Memory for Embedded Multicore Systems | Cesare Ferri (Brown University), Samantha Wood (Bryan Mawr College), Tali Moreshet (Swartmore College), Iris Bahar, and Maurice Herlihy (Brown University) | |
| 12:45 - 14:00 Lunch | ||
| 14:00 - 16:00 Session 2 | Compilation and Runtime Systems | Chair: Carol Thomson Eidt, Microsoft |
| Split Register Allocation: Linear Complexity Without the Performance Penalty | Boubacar Diouf, Albert Cohen (INRIA), Fabrice Rastello (ENS Lyon), and John Cavazos (Univ. of Delaware) | |
| Trace-Based Data Layout Optimizations for Multi-Core Processors | Olga Golovanevsky, Alon Dayan, Ayal Zaks (IBM Israel) and David Edelsohn (IBM) | |
| Buffer sizing for self-timed stream programs on heterogeneous distributed memory multiprocessors | Paul Carpenter, Alex Ramirez and Eduard Ayguade (BSC Barcelona) | |
| Automatically tuning sparse matrix-vector multiplication for | Alexander Monakov and Arutyun Avetisyan (Russian Academy of Science), Anton Lokhmotov (Imperial College London) | |
| GPU architectures | ||
| Break | ||
| 16:30 - 18:30 Session 3 | Reconfigurable and Customized Architectures | Chair: Cristina Silvano, Politecnico di Milano |
| Virtual Ways: Efficient Coherence for Architecturally Visible Storage in Automatic Instruction Set Extensions | Samuel Burri, Theo Kluter, Philip Brisk, Edoardo Charbon and Paolo Ienne (EPFL Lausanne) | |
| Accelerating XML query matching through custom stack generation on FPGAs | Roger Moussalli, Mariam Salloum, Walid Najjar, and Vassilis Tsotras (Univ. of California Riverside) | |
| An Application-aware Load Balancing Strategy for Network Processors | Rainer Ohlendorf, Michael Meitinger, Thomas Wild, and Andreas Herkersdorf (TU Munich) | |
| Memory-Aware Application Mapping on Coarse Grain Reconfigurable Arrays | Yongjoo Kim, Jongeun Lee, Aviral Shrivastava, Jonghee Yoon, and Yunheung Paek (Arizona State Univ.) | |
| Tue Jan 26 | ||
| 8:45 - 10:00 Keynote 2 | Larrabee: A Many-Core Architecture for Visual Computing | Roger Espasa, Principal Engineer, Intel |
| Break | ||
| 10:30 - 12:30 Session 4 | Multicore Efficiency, Reliability and Power | Chair: Thomas Gross, ETH Zuerich |
| Maestro: Orchestrating Lifetime Reliability in Chip Multiprocessors | Shuguang Feng, Shantanu Gupta, Amin Ansari, and Scott Mahlke (Univ. of Michigan) | |
| Combining Locality Analysis with Online Proactive Job Co-Scheduling in Chip | Yunlian Jiang, Kai Tian, and Xipeng Shen (College of William and Mary) | |
| RELOCATE: Register File Local Access Pattern Redistribution Mechanism for Power and Thermal Management in Out-of-Order Embedded Processors | Houman Homayoun, Aseem Gupta, Alex Veidenbaum, and Fadi Kurdahi (Univ. of California Irvine) | |
| Performance and Power Aware CMP Thread Allocation Modeling | Yaniv Ben-Itzhak, Israel Cidon, and Avinoam Kolodny (Technion Israel) | |
| 12:30 - 13:30 Lunch | ||
| 13:30 - 14:30 Panel | "Heterogenous vs. Homogenous Computing" | Yale Patt (UT Austin), Roger Espasa (Intel), Hank Hoffmann (Tilera/MIT), Walid Najjar (UC Riverside) |
| Moderator: Paolo Faraboschi, HP Labs | ||
| 14:30 - 17:30 Guided Pisa Tour | ||
| 19:00 Banquet | ||
| Wed Jan 27 | ||
| 8:30 - 10:30 Session 5 | Memory Organization and Optimization | Chair: Jim Dehnert, Google |
| Multi-Level Hardware Prefetching using Low Complexity Delta Correlating Prediction Tables with Partial Matching | Marius Grannaes, Magnus Jahre and Lasse Natvig (Norwegian Institute of Science and Technology) | |
| Scalable Shared Cache Management by Containing Thrashing Workloads | Yuejian Xie and Gabriel H. Loh (Georgia Tech) | |
| SRP: Symbiotic Resource Partitioning of the Memory Hierarchy in CMPs | Shekhar S. Srikantaiah and Mahmut T. Kandemir (Penn State University) | |
| DIEF: An Accurate Interference Feedback Mechanism for Chip Multiprocessor Memory Systems | Magnus Jahre, Marius Grannaes and Lasse Natvig (Norwegian Institute of Science and Technology) | |
| Break | ||
| 11:00 - 13:00 Session 6 | Programming and Analysis of Accelerators | Chair: Albert Cohen, INRIA |
| Tagged Procedure Calls (TPC ): Efficient runtime support for task-based parallelism on the Cell Processor | George Tzenakis, Konstantinos Kapelonis, Michail Alvanos, Konstantinos Koukos, Dimitrios Nikolopoulos, and Angelos Bilas (FORTH, Greece) | |
| Analysis of Task Offloading for Accelerators | Roger Ferrer, Vicen Beltran (BSC Barcelona), Marc Gonzalez, Xavier Martorell (UPC Barcelona), and Eduard Ayguade (BSC Barcelona) | |
| Offload -- Automating code | Pete Cooper, Uwe Dolinsky (Codeplay), Alastair F. Donaldson (Oxford Univ.), Andrew Richards, Colin Riley, and George Russell (Codeplay) | |
| migration to heterogeneous multicore systems | ||
| Computer Generation of Efficient Software Viterbi Decoders | Frederic de Mesmay, Srinivas Chellappa, Franz Franchetti, and Markus Pschel (Carnegie Mellon Univ.) | |
| 13:00 - 13:15 Closing/ awards | ||