Description:

Embedded systems are often severely constrained when it comes to form-factor

requirements and energy consumption.

Unfortunately, the 'one-size-fits-all' paradigm used in general-purpose

computers waste microarchitecture and memory resources and leads to designs

that are far from optimal. This is especially a problem for embedded

computers. There has been a lot of work recently on adaptable architectures

that aim at dynamically adjust resources to the computational needs. One

such example is the recent work on adaptable cache systems where the size of

the cache is changed based on working set size predictions. Unfortunately,

most of the work in the open literature has focussed on desktop and server

applications.



The goal of the proposed project is severfold:



- Analysis of dynamic resource needs of embedded applications

- Design principles for adaptable memory hierarchies

- Design principles for adaptable microarchitectures



As a first step, we will agree on a baseline architecture and benchmark

suite so as to maximize the relevance for the embedded domain. This includes

agreeing on an evaluation methodology (e.g., simulation platform). Of

course, this work will have strong ties to the 'common simulation platform"

project within HIPEAC.



As a second and third step, we will characterize the computational resource

needs of the application suite to identify bottlenecks and time-dependent

needs. As for the work on adaptable memory hierarchies, we wish to analyze

the bottlenecks of the embedded applications, that are responsible for

more needs of resources at microarchitectural level and at memory hiearchy

level. Based on such analysis, we can propose mainly run-time

(and possibly compile-time hint) solutions to properly allocate available

resources or to shut down resurces of the chip that are not used. Metrics

that we wish to improve may regard both perfomance and low-power as well

as area-efficiency.



Concretely, we are particularly interested in researching the following

topics:



- Techniques that exploit the fact that the operand size varies across

applications and within an application

as noted in previous work.

- Further develop ongoing work on compression technique so as to improve

resource utilization for memory and interconnects

- New approaches to phase detection and prediction techniques to control

adaptivity

Nature:
Research cluster

Total funding:
Requested: € 14800
Granted: € 5000

Including fellowship funding:
Requested: € 0
Granted: € 0

Description of how the funding will be used:

For Chalmers:



4 shorter visits (3 days each) at Siena and Pisa:



Accommodation: 12 hotel nights (1200 EU)

Traveling: 4 round-trip flights (3200 EU)



2 one-week visits



Accommodation: 14 hotel nights (1400 EU)

Traveling: 2 round-trip flights (1600 EU)



For Pisa/Siena (the same):



4 shorter visits (3 days each) at Siena and Pisa:



Accommodation: 12 hotel nights (1200 EU)

Traveling: 4 round-trip flights (3200 EU)



2 one-week visits



Accommodation: 14 hotel nights (1400 EU)

Traveling: 2 round-trip flights (1600 EU)

Duration of the funding:
Requested: 12 month(s)
Granted: 12 month(s), starting on: Tue, January 1, 1980

Participating members:
STENSTROM Per (Chalmers University of Technology) (--member--)
PRETE Antonio (University of Pisa) (--member--)
GIORGI Roberto (University of Siena) (--member--)
FOGLIA Pierfrancesco (University of Pisa) (--member--)
BARTOLINI Sandro (University of Siena) (--member--)

Other people collaborating:

- Martin Thuresson (Chalmers)

- Magnus Sjallander (Chalmers)

- Charlotta Baath (Chalmers)

- Daniele Mangano (Pisa)

- Paolo Bennati (Siena)

- Zdravko Popovic (Siena)