Research challenge:

The shift towards multi-core architectures poses several challenges for computer architects. With each new technology generation, there will be a significant increase of the number of transistors. The question is how computer architects can establish computational structures that can transform the increase in transistors into an equal increase in computational performance efficiency. This challenge must be attacked from several fronts, namely, the basic architecture of each processor (core) to increase single thread performance, via the architecture of the memory system, to a holistic approach to support emerging programming models that aim at reducing the efforts the programmers have to invest in designing software amenable to multi-core architectures. As a consequence, this cluster will be engaged in advancing state-of-the-art in the following areas:

Initial research topics:

• Processor architecture
• Memory hierarchy
• Technology impact on architecture
• Application impact on architecture
• Architecture support for parallel programming models
• Power/performance evaluation methodologies

Planned activities:

• Joint research
• Annual workshop at the HiPEAC conference

Coordinating partner: CHALMERS