Research challenge:

Multi-core and multiprocessor systems that can scale to large sizes critically depend on efficient inter-processor communication. The mandate of this cluster is to promote the architecture of circuits, systems, and software used to enable the interconnection of and communication among multiple cooperating processing cores, engines, memories, storage, and input/output devices and subsystems. Interdependent and conflicting goals have to be achieved: low latency, low power, low cost, high throughput, high versatility, and QoS guarantees. Open questions still remain in some areas, while, in others, old solutions must be revised in view of new requirements for scale (number of nodes), switch and link parameters (networks-on-chip), and tightness of coupling between the processors and the network.

Initial research topics:

• Networks-on-Chip (NoC), System Interconnection Networks:
  
  • technology – wires, drivers, buffer memories, switches;
  • network – routing, flow & congestion control, scheduling, quality of service (QoS);
  • interfaces – processor-NoC, accelerator-NoC, cache-NoC, memory chip interfaces, NoC-SAN, SAN-LAN/WAN;
  • virtualization, reliability, reconfigurability support;
  • power consumption reduction.
• Inter-processor communication:
  
  • transport means for communication paradigms – shared-memory, message-passing;
  • network routing and addressing support for data and thread placement, migration, protection, virtualization;
  • runtime system, and support for explicit software control – deterministic computing.

Planned activities:

• Common and jointly-used prototyping platforms (esp. FPGA-based);
• Use common chip design and simulation libraries;
• Coordinated and joint research, in order to build up the European interconnects research community.

Coordinating partner: FORTH