Design methodology and tools

Research challenge:

Electronic design automation (EDA) methodology and tools are key enablers for many HiPEAC research activities, such as multi-core and NoC architectures, or reconfigurable systems. In the light of moving towards 65nm and 45nm CMOS technologies, and thus the urgent need for higher design productivity, EDA is currently aiming at a new abstraction level: Electronic System Level (ESL). ESL focuses on system design aspects 'beyond RTL', e.g. efficient HW/SW modelling and partitioning, mapping applications to MPSoC architectures, ASIP design, etc. These and other research topics are being addressed in the 'Design methodology and tools' cluster. While ESL is currently mostly driven by the embedded system design community, due to the need to design efficient application specific systems with very limited resources (and thus with a higher acceptance of automation and tools), it can strongly benefit from many recent developments in the high-performance community (such as fast simulation, efficient compilation etc.), and vice versa. Therefore, another important goal of this cluster is to establish a closer link between these communities. Besides the regular cluster meetings, this is being implemented e.g. by coupling of existing platforms and tools, so as to achieve new heights in design productivity.

Scientific issues:

• Design methodology and tools driven by the trend towards multiprocessor system-on-chip (MPSoC) architectures.
• Applications include: wireless communications, multimedia, automotive.
• Very high efficiency goals (MIPS/Watt or Joule/bit), therefore programmable, yet application-specific and heterogeneous MPSoCs.
• Currently shift towards Electronic System Level (ESL) design methodologies, will provide the required next productivity boost beyond RTL design.
• Key for managing the complexity of today's and future digital chip designs in advanced CMOS technologies (45nm, 32nm, and beyond).

Research topics:

• Embedded processor design: ASIP design, design space exploration, configurable and reconfigurable processors, SW tools generation, retargetable compilation, processor/compiler co-design, loop parallelization, template based ASIP design, instruction set extensions, ultra-low power ASIPs, open source processor cores .
• MPSoC modelling and verification: modelling languages, SystemC based modelling, verification and design, high-speed instruction set simulation, virtual platforms, path from model to implementation, NoC simulation.
• MPSoC programming: application-to-architecture mapping, RTOS, task graph scheduling, sequential-to-parallel code generation, benchmarking.
• MPSoC HW/SW architectures: SW performance estimation, HW/SW integration, tightly coupled processor architectures, memory hierarchy, HW/SW interface synthesis, fault tolerance, loop transformations.

Major cluster activities:

• Cluster meetings: Three regular cluster meetings were held in 2008 Several new members have been accepted, among them associate members from USA and Japan. Thanks to a relatively high number of company members, there is a good degree of academia/industry interaction.
• Web site: A cluster web site (at www.hipeac.net) has been set up. It contains e.g. member research profiles, supporting material, as well as cluster meeting minutes.
• HiPEAC workshops and schools: Cluster members attended major HiPEAC events such as the ACACES summer school and various industrial workshops.
• Bilateral research meetings: Numerous bilateral meetings took place in 2008 in order to discuss particular research issues.
• MPSoC Forum: The cluster provided sponsorship for the MPSoC Forum (Aachen, June 2008). The MPSoC Forum (www.mpsoc-forum.org) is the premier international event in application specific MPSoC architectures and design tools.
• RAPIDO workshop: Together with people from the HiPEAC simulation cluster, a new workshop on simulation and architecture exploration has been organized, scheduled to take place at the HiPEAC conference in Jan 2009.
• ECSI workshops: Aachen's research results on Virtual Platform technology, developed jointly with CoWare, have been successfully demonstrated at various ECSI workshops.
• Infineon MPSoC workshop: German HiPEAC partners (Aachen, Erlangen, Augsburg) have organized a joint workshop with Infineon Technologies (Nov 2008) in Munich.
• Industry internships: Students from Aachen have performed 6 months industry internships at ACE and Infineon.
• DATE special session: A University Booth and a MPSoC programming special session were organized during the DATE 2009 conference.

Coordinating partner: RWTH Aachen