Research challenge:

One of the key challenges of future multi-core architectures is programmability and scalability. As compilers link the code written by programmers to the underlying parallel hardware, this cluster has a pivotal role to play. It will focus on versatility by adapting the user code to the ever changing underlying hardware. It will pursue a system wide perspective on adapting programs, and more generally workloads, to both short-term architecture variation, such as cache misses, and longer-term changes, such as the increasing number of processors available. It will include the following topics.

Initial research topics:

• System adapts to hardware
  
  • Iterative compilation: auto-tuning/parallelizing applications to new parallel hardware
  • Machine learning based compilation: using machine learning to learn new optimization strategies for multi-cores
  • Dynamic compilation and virtual machines: combining ahead of time optimization plus JIT compilation for Java and .NET-like applications on multi-cores
• Hardware adapts to system
  
  • Compiler/runtime fusion: Both make resource and scheduling decision. Combining allows static knowledge about future behavior and previous dynamic behavior to be exploited.
  • Resource-aware compilation. Use knowledge of the program to configure the processor to maximize ED2. Specialize the ISA to give ASIP solutions.
  • Reconfiguration: dynamically change the processor structure based on either off-line analysis or dynamic knowledge.

Planned activities:

• Co-organize a workshop with CPC (International Workshop on Compilers for Parallel Computing) January 2009.
• Linking together the European compiler community via joint papers and workshops.
• Interacting with other clusters to develop a system wide view of performance optimization.

Coordinating partner: UEDIN